The Mobile Industry Processor Interface (MIPI®) Alliance has been defining standards for serial interfaces, including physical layer (PHY) standards that may be used in mobile devices to provide high bandwidth connections between devices and peripherals within mobile devices. The MIPI standards include the D-PHY standard (referred to herein as MIPI D-PHY, or DPHY) that employs a signaling scheme which requires a dedicated clock lane to provide a receiving device with timing information used by a transmitting device to transmit data. The MIPI standards include the M-PHY standard (referred to herein as MIPI M-PHY, or MPHY) that employs a signaling scheme in which the transmitter embeds the timing information in the transmitted data and the receiver extracts the timing information using a phase-locked loop (PLL) to provide a receive clock.
The use of a dedicated clock lane requires using at least one extra conductor and the use of PLLs to extract clocks embedded in the data lanes increases the complexity of the receiver circuitry, particularly when the PLLs must rapidly synchronize on received data signals.